As predicted by Gordon E.
Moore in , the performance of computer processors increased at an e…. Big Data has been much in the news in recent years, and the advantages conferred by the collectio…. Parallel computing has been the enabling technology of high-end machines for many years.
Advances in Computers, Volume 114
Now, it …. Cloud computing offers many advantages to researchers and engineers who need access to high perfo…. Single processing units have now reached a point where further major improvements in their perfor…. In many computer users were exploring the opportunities and the benefits of the massive para…. In the last decade, parallel computing technologies have transformed high-performance computing.
Parallel computing technologies have brought dramatic changes to mainstream computing; the majori…. During the last decade parallel technologies have completely transformed main stream computing. View on ScienceDirect.
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Institutional Subscription. Free Shipping Free global shipping No minimum order. Monte Carlo simulations are used to tackle a wide range of exciting and complex problems, such as option pricing and biophotonic modelling.
Alongside these accelerators, Multilevel Monte Carlo techniques can be harnessed to further hasten simulations. However, researchers and application developers must invest a great deal of effort to design, optimise and test such Monte Carlo simulations. Furthermore, these models often have to be rewritten from scratch to target new hardware accelerators. This paper presents Neb, a Domain Specific Language for describing and generating Multilevel Monte Carlo simulations for a variety of hardware architectures.
Neb can be used to solve stochastic equations or to generate paths for analysis with other tools. Furthermore, the energy efficiency of these accelerators is compared, revealing FPGAs to be 8.
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Commonly used in software design, assertions are statements placed into a design to ensure that its behaviour matches that expected by a designer. Although assertions apply equally to hardware design, they are typically supported only for logic simulation, and discarded prior to physical implementation. We propose a new HDL-agnostic language for describing latency-insensitive assertions and novel methods to add such assertions transparently to an already placed-and-routed circuit without affecting the existing design.
We also describe how this language and associated methods can be used to implement semi-transparent exception handling. The key to our work is that by treating hardware assertions and exceptions as being oblivious or less sensitive to latency, assertion logic need only use spare FPGA resources. Experimental evaluation shows zero impact on critical-path delay, even on large benchmarks operating above MHz, at the cost of a small power penalty.
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In this work we propose an architecture and an automated customisation method to detect and optimise the architecture for block diagonal sparse matrices. This problem leads to a large sparse system of linear equations with block diagonal matrix which is typically solved using an iterative method such as the Preconditioned Conjugate Gradient. The efficiency of the proposed architecture combined with the effectiveness of the proposed customisation method reduces BRAM resource utilisation by as much as 10 times, while achieving identical throughput with existing state of the art designs and requiring minimal development effort from the end user.
In the context of the Finite Element Method, our approach enables the solution of larger problems than previously possible, enabling the applicability of FPGAs to more interesting HPC problems. This paper presents a novel approach for automatic optimisation of reconfigurable design parameters based on knowledge transfer.
The key idea is to make use of insights derived from optimising related designs to benefit future optimisations. We show how to use designs targeting one device to speed up optimisation of another device. The proposed approach is evaluated based on various applications including computational finance and seismic imaging. To handle the stringent performance requirements of future exascale-class applications, High Performance Computing HPC systems need ultra-efficient heterogeneous compute nodes.
To reduce power and increase performance, such compute nodes will require hardware accelerators with a high degree of specialization. Ideally, dynamic reconfiguration will be an intrinsic feature, so that specific HPC application features can be optimally accelerated, even if they regularly change over time. In the EXTRA project, we create a new and flexible exploration platform for developing reconfigurable architectures, design tools and HPC applications with run-time reconfiguration built-in as a core fundamental feature instead of an add-on.
EXTRA covers the entire stack from architecture up to the application, focusing on the fundamental building blocks for run-time reconfigurable exascale HPC systems: new chip architectures with very low reconfiguration overhead, new tools that truly take reconfiguration as a central design concept, and applications that are tuned to maximally benefit from the proposed run-time reconfiguration techniques.
Ultimately, this open platform will improve Europe's competitive advantage and leadership in the field. This paper introduces cycle-reconfigurable modulesthat enhance FPGA architectures with efficient support fordynamic data accesses: data accesses with accessed data size andlocation known only at runtime.
The proposed module adoptsnew reconfiguration strategies based ondynamic FIFOs,dynamiccaches, anddynamic shared memoriesto significantly reduceconfiguration generation and routing complexity. The integrated moduletakes less than the chip area of 39 CLBs, and reconfiguresthousands of runtime connections in 1. Applications for large-scale sorting, sparse matrix-vector multiplication, and Mem-cached are developed. The proposed modules enable 1. Applications with irregular data accesses, whichpreviously cannot be efficiently supported in hardware, canbe efficiently mapped into EURECA architectures.
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